I am doing a wire spooling application using a D-260 cpu, F2-8AD4DA-2 16 bit 8 ch in / 12 bit 4 ch out 0-10 vdc board. The system will consist of a payoff unit using a 10hp ac flux vector drive, a dancer, and a takeup unit suing a 2hp ac flux vector drive. What I am tinkering around with is this: Using the speed pot for an overall master line speed reference signal (0-10 vdc) controlling the takeup speed. What I want to do is use the pid as a trim. For example if the takeup is running at 2000 fpm at 5 vdc reference, naturally the payoff needs to run at the same 2000 fpm. But assuming that 2000 fpm is 5 vdc reference on the payoff as well. The dancer (0-10 vdc) is the input to the pid algorithm (PV). I would like for the 5 volts dc going to the payoff to be made up of approx 90% speed pot ref and 10% pid. Specifically bipolar pid where if the SP is in the middle ie.. 32768=SP (16bit). I can cap the limit of the pid to around 10000 counts or 1.53 volts positive and -10000 counts negative. That way I would have from the 5 volts of reference going to the VFD a maximum of 1.53 of those volts would be from the pid, and the other 3.47 volts would be from the speed pot. What I am running into is by adding the maximum 10000 counts to the maximum value of the speed pot of 65535 (10v) that puts me over the limit. Conversely on the low end of the scale when the negative pid limit of -10000 is added to the speed pot reference I actually go below 0 and the counts roll over. I am currently using a CMPR instruction and watching if the converted Real value goes above or below the thresholds and doing an "ignore" values bit. Is there an easier way to do what I am wanting to do?
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